TTC WEB PAGETTC UPGRADE HOMENEW SYSTEMTTC RECEIVER CRATERF2TTC SPECIFICATIONSRF_Rx & RF_Tx

RF2TTC INTERFACE MODULE

Last updated: 18/03/2011 15:35

 

DOCUMENTS:

The RF2TTC module will act as an interface between the AB/RF optical receiver modules and the TTC system within the experiments. It will replace the TTCmi and bring some new functionalities like remote monitoring and control...

The RF2TTC is converting the three 40.078MHz  Bunch Clocks (BC) and the two orbit signals from the RF optical receivers to ECL signals, and proposes various adjustments on each signal before making them available for the in-detector TTC electronics.

Form Factor:

The board is a 6U-4TE VME64x module.

Power supplies:

The standard voltages available on the power supplies of the TTC crates are +5V, +/-12V, +3.3V and 48V. The ALICE CTP crates, however, have no 48V.

To keep the compatibility between all the users, the RF2TTC will thus only use the following voltages:

As the VME specification allows only 1.5A per pin, the maximum current per board will be 9A for the 5V and the +3V3, and 1.5A per +/-12V each). 

Technologies:

Inputs and Outputs:

 Inputs:

Two types of inputs are available on the RF2TTC Front Panel:

The RF timing inputs are directly taken from the RF Rx modules. As 3 BC types and 2 Orbit types can be delivered by these modules, 5 inputs are foreseen in the front panel. To simplify,  ‘Orbit’ is used for Frev or Orbit indistinctively.

 Outputs:

It is proposed to provide 1 pair of ECL and NIM outputs per input, plus one pair of MAIN BC (ECL and NIM) and MAIN ORBIT (ECL and NIM). The connectors used for the outputs are Lemos.

Bunch Clocks:

The direct pairs of BC outputs are just simply the converted inputs, cleaned by a QPLL. It is possible to switch remotely the BC sources from inputs to the internal clock to work in stand-alone mode. The phase of each BC signal can be independently adjusted.

The MAIN BC is multiplexed between BC1, BC2, BCref and the internal clock.

Each ECL output is AC-coupled.

Orbit:

The direct pairs of Orbit are synchronized to their relative Bunch Clocks (BC1 for the Orbit of ring1 and BC2 for the Orbit of ring2) and stretched with an adjustable length. To ensure a stable synchronization, the input orbit phases are also adjustable, as well as the orbit outputs. It is as well possible to switch the Orbit sources from input to internal counters.

 The MAIN ORBIT is synchronized to the MAIN BC, and multiplexed between Orb1, Orb2 and an adjustable internal counter running at the MAIN BC frequency.

Each ECL output is NECL-DC coupled.

Control Functions:

 

VME registers:

The CSR space (AM 0x2F) will contain the board ID as well as the BAR (Board Address Register).

The other access types will be reduced to D32/A32 (AM 0x09). To simplify the firmware, the board will not answer to D8 and D16 requests.

The mapping is cut in various blocks, one per each output, plus the BST interface and some general purpose registers. The blocks do not have consecutive addresses. Each block has a simple offset to ease the access and to allow some reserved space.

 The interrupt lines are wired and thus available. Nevertheless, as CMS and LHCb may want to use VME masters handling interrupts, they should not be necessary in normal modes. They may be implemented as flags.

 The Board address (8 bits) is manually configurable using rotary switches. The address 0 is not considered as a manual address, but indicates that the Board address is set by the geographical addressing facility.

Block Diagram (FINAL 02/05/06):

 

Main

 

Last Updated by Sophie BARON on 18/03/2011 15:35

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